Module `Vectorize_utils.Memory_access`

module Init_or_assign : sig ... end

type desc =

| Alloc
| Arbitrary
| Read of {
1. width_in_bits : Vectorize_utils.Width_in_bits.t;
2. addressing_mode : Arch.addressing_mode;
3. is_mutable : bool;
4. is_atomic : bool;
}
| Write of {
1. width_in_bits : Vectorize_utils.Width_in_bits.t;
2. addressing_mode : Arch.addressing_mode;
3. init_or_assign : Vectorize_utils.Memory_access.Init_or_assign.t;
}
| Read_and_write of {
1. width_in_bits : Vectorize_utils.Width_in_bits.t;
2. addressing_mode : Arch.addressing_mode;
3. is_atomic : bool;
}

type t

val create : 
  ?first_memory_arg_index:int ->
  Vectorize_utils.Memory_access.desc ->
  Vectorize_utils.Memory_access.t

val desc : 
  Vectorize_utils.Memory_access.t ->
  Vectorize_utils.Memory_access.desc

val first_memory_arg_index : Vectorize_utils.Memory_access.t -> int

val alignment_in_bytes : Vectorize_utils.Memory_access.t -> int

Base address of memory access t is guaranteed to be aligned to at least alignment_in_bytes t.

Module Vectorize_utils.Memory_access