jon.recoil.org

Module Amd64_simd_defs

type ext =
  1. | SSE
  2. | SSE2
  3. | SSE3
  4. | SSSE3
  5. | SSE4_1
  6. | SSE4_2
  7. | POPCNT
  8. | LZCNT
  9. | PCLMULQDQ
  10. | BMI
  11. | BMI2
  12. | AVX
  13. | AVX2
  14. | F16C
  15. | FMA
type reg =
  1. | RAX
  2. | RDI
  3. | RCX
  4. | RDX
  5. | XMM0
type temp =
  1. | R8
  2. | R16
  3. | R32
  4. | R64
  5. | M8
  6. | M16
  7. | M32
  8. | M64
  9. | M128
  10. | M256
  11. | MM
  12. | XMM
  13. | YMM
  14. | VM32X
  15. | VM32Y
  16. | VM64X
  17. | VM64Y
type loc =
  1. | Pin of Amd64_simd_defs.reg
  2. | Temp of Amd64_simd_defs.temp array
type loc_enc =
  1. | RM_r
  2. | RM_rm
  3. | Vex_v
  4. | Implicit
  5. | Immediate
type res =
  1. | Res_none
  2. | First_arg
  3. | Res of Amd64_simd_defs.arg array
type legacy_prefix =
  1. | Prx_none
  2. | Prx_66
  3. | Prx_F2
  4. | Prx_F3
type legacy_rex =
  1. | Rex_none
  2. | Rex
  3. | Rex_w
type legacy_escape =
  1. | Esc_none
  2. | Esc_0F
  3. | Esc_0F38
  4. | Esc_0F3A
type vex_map =
  1. | Vexm_0F
  2. | Vexm_0F38
  3. | Vexm_0F3A
type prefix =
  1. | Legacy of {
    1. prefix : Amd64_simd_defs.legacy_prefix;
    2. rex : Amd64_simd_defs.legacy_rex;
    3. escape : Amd64_simd_defs.legacy_escape;
    }
  2. | Vex of {
    1. vex_m : Amd64_simd_defs.vex_map;
    2. vex_w : bool;
    3. vex_l : bool;
    4. vex_p : Amd64_simd_defs.legacy_prefix;
    }
type rm_reg =
  1. | Reg
  2. | Spec of int
type enc = {
  1. prefix : Amd64_simd_defs.prefix;
  2. rm_reg : Amd64_simd_defs.rm_reg;
  3. opcode : int;
}
type imm =
  1. | Imm_none
  2. | Imm_reg
  3. | Imm_spec
type 'id instr = {
  1. id : 'id;
  2. ext : Amd64_simd_defs.ext array;
  3. args : Amd64_simd_defs.arg array;
  4. res : Amd64_simd_defs.res;
  5. imm : Amd64_simd_defs.imm;
  6. mnemonic : string;
  7. enc : Amd64_simd_defs.enc;
}
val equal_reg : Amd64_simd_defs.reg -> Amd64_simd_defs.reg -> bool
val equal_temp : Amd64_simd_defs.temp -> Amd64_simd_defs.temp -> bool
val equal_loc : Amd64_simd_defs.loc -> Amd64_simd_defs.loc -> bool
val temp_is_reg : Amd64_simd_defs.temp -> bool
val loc_allows_reg : Amd64_simd_defs.loc -> bool
val loc_allows_mem : Amd64_simd_defs.loc -> bool
val loc_is_pinned : Amd64_simd_defs.loc -> Amd64_simd_defs.reg option
val arg_is_implicit : Amd64_simd_defs.arg -> bool
val ext_to_string : Amd64_simd_defs.ext -> string
val exts_to_string : Amd64_simd_defs.ext array -> string
module Layout : sig ... end
val loc_register_width : Amd64_simd_defs.loc -> Amd64_simd_defs.Layout.reg option